1. Field of the Invention
The present invention relates generally to semiconductor devices and methods for their fabrication. More particularly, the present invention relates to hardening of gate oxides in semiconductor devices by nitrogen implantation and anneal subsequent to dopant implantation and activation to increase the dielectric constant thereof and, accordingly, decrease the effective thickness of the gate oxide.
2. State of the Art
Higher performance, enhanced reliability and greater packaging density are constant goals of the semiconductor industry. However, as components of integrated circuits become increasingly smaller to meet these goals, it has become more and more difficult to produce semiconductor devices capable of reliable, long-term operation, particularly in view of the operational stresses each component of a state of the art semiconductor device must endure. For instance, as surface P-channel transistors decrease in size, the size and thickness of the gate oxides included in such transistors must also decrease. However, as gate oxide thickness continues to be compressed, the gate oxides become increasingly permeable to dopants included in the overlying polysilicon gate electrodes. Further, they become less resistant to hot electron degradation and more susceptible to breakdown voltages below normal operating voltages.
To address these problems, various processes for hardening gate oxides and, accordingly, reducing the effective thickness thereof, have become highly beneficial to the fabrication of state of the art semiconductor devices. For instance, a method well known in the art for forming hardened gate oxides involves implanting nitrogen into a semiconductor substrate (e.g., a silicon substrate) followed by thermal oxide growth on the top surface of the substrate. During the thermal oxide growth, oxynitride is formed at the gate oxide/substrate interface. As oxynitride has a higher dielectric constant than pure oxide, the resultant oxide effective thickness is smaller than it would be without the nitrogen implantation.
Another conventional method for forming hardened gate oxides involves implanting nitrogen into the gate oxide after formation thereof. The method includes providing a semiconductor substrate, forming a gate oxide layer over the semiconductor substrate and subjecting the gate oxide layer to a nitrogen implantation treatment. The nitrogen penetrates the top surface of the gate oxide layer but does not initially bind therewith. As such, the nitrogen implantation is followed by an oxidative anneal which results in the formation of oxynitride in the gate oxide layer and at the gate oxide/substrate interface. Again, due to the increased dielectric constant of the oxynitride relative to pure oxide, the resultant gate oxide layer has a smaller effective thickness than it would have without the nitrogen implantation.
In addition to having an increased dielectric constant, relative to nonhardened devices, gate oxides hardened by known methods are generally less permeable to dopants included in polysilicon electrodes, more resistant to hot electron degradation and less susceptible to breakdown voltages below normal operating voltages. However, known processes for hardening gate oxides also have drawbacks. For example, in order to prevent diffusion of dopants from the polysilicon electrode into and through the gate oxide, known hardening processes often provide a high concentration of nitrogen at the interface of the gate oxide and the underlying semiconductor substrate. However, as is known to those of ordinary skill in the art, excessive nitrogen at the gate oxide/substrate interface significantly degrades transistor performance.
Accordingly, in terms of device performance and reliability, it has been found to be advantageous to fabricate a gate oxide layer having a relatively small nitrogen concentration at the gate oxide/substrate interface with the bulk of the nitrogen concentration being located at the polysilicon/gate oxide interface. The relatively large nitrogen concentration at the polysilicon/gate oxide interface effectively prevents diffusion of dopants from the polysilicon electrode and into and through the gate oxide layer while the relatively small nitrogen concentration at the gate oxide/substrate interface confers resistance to hot electron degradation without substantially affecting device performance. Further, in addition to the nitrogen concentration at the gate oxide/substrate interface, it has been found to be advantageous for a relatively small concentration of nitrogen to be located within the gate oxide to aid in increasing the dielectric constant of the gate oxide and, accordingly, in reducing the effective thickness thereof While some known processing techniques (e.g., rapid plasma nitridation (RPN) and decoupled plasma nitridation (DPN)) provide transistors including a gate oxide having a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface, such techniques are often prohibitively expensive.
At least one method has been developed in an attempt to provide a transistor including a gate oxide having some of the above-stated characteristics. U.S. Pat. No. 6,017,808 to Wang et al. (hereinafter “the '808 patent”) describes a method for hardening a gate oxide designed to provide a transistor wherein a large peak of nitrogen exists within the polysilicon and gate oxide layers at the polysilicon/gate oxide interface, while a relatively smaller nitrogen peak occurs within the gate oxide layer and the underlying semiconductor substrate at the gate oxide/substrate interface. To achieve this structure, the method of the '808 patent requires implanting nitrogen through a first polysilicon layer and into the gate oxide layer followed by an anneal step. After the implantation and annealing steps, a first, relatively large, nitrogen peak occurs entirely within the first polysilicon layer, a second, relatively smaller, nitrogen peak occurs at the polysilicon/gate oxide interface, and a third, relatively smaller still, nitrogen peak occurs at the gate oxide/substrate interface. However, due to its magnitude, the first nitrogen peak located entirely within the first polysilicon layer is somewhat counterproductive because it retards activation of subsequently implanted dopants, such as boron, within the first polysilicon layer. Therefore, the method of the '808 patent requires removal of the portion of the first polysilicon layer which includes the first nitrogen peak without removing the portion of the first polysilicon layer which includes the second nitrogen peak (i.e., the peak occurring at the polysilicon/gate oxide interface) to form a second polysilicon layer. Once the portion of the first polysilicon layer including the first nitrogen peak is removed to form the second polysilicon layer, a third, nitrogen-free polysilicon layer may be optionally formed over the second, nitrogen-implanted, polysilicon layer.
As will be readily appreciated, achieving the structure disclosed in the '808 patent using the methods described therein is at best difficult, particularly in light of the continually decreasing thickness of polysilicon electrodes included in state of the art semiconductor devices. One of the most troublesome aspects of the method described in the '808 patent is the need to remove only the portion of the nitrogen-implanted polysilicon layer including the first nitrogen peak. The reference teaches that this task may be accomplished using known wet etch, dry etch, or chemical mechanical processing techniques. However, the polysilicon layers used for polysilicon electrodes in state of the art transistors are exceedingly thin. The polysilicon electrodes of some state of the art devices may be as thin as seven or fewer molecular monolayers, and known etching and polishing processes are difficult to control with sufficient precision to remove only predetermined portions of material layers of such minute thicknesses. Moreover, in this context, the polysilicon layer will include varying concentrations of nitrogen at any given depth, and as the nitrogen concentration varies, the etch rate will also vary, making precise control of the etching process even more difficult. Thus, removing only the portion of the first polysilicon layer, including the first nitrogen peak, is extremely difficult, and known removal processes will most likely result in removal of too much or too little polysilicon material, resulting in transistors exhibiting impaired performance or reduced reliability.
A further problem, that of cross-diffusion, is encountered when a metal gate strap (e.g., a metal silicide layer) is disposed over the polysilicon layer. Cross-diffusion occurs, for example, in surface P-channel transistors having both P-type and N-type dopants that may diffuse across the silicide/polysilicon interface and contaminate underlying layers. A relatively large concentration of nitrogen at the silicide/polysilicon interface may substantially prevent dopant diffusion across the interface. However, known processing techniques do not provide semiconductor devices having a relatively large concentration of nitrogen at the silicide/polysilicon interface. In particular, a transistor fabricated utilizing the methods described in the '808 patent would not alleviate cross-diffusion as the portion of the first polysilicon layer including the first nitrogen peak is removed therefrom. If, in later processing, a silicide layer were to be formed over the second polysilicon layer, there would be insufficient nitrogen at the silicide/polysilicon interface to effectively substantially prevent cross-diffusion across the interface. As an alternative embodiment, the '808 patent describes a method wherein a third, nitrogen-free, polysilicon layer may be formed over the second polysilicon layer. If, in later processing, a metal gate strap were to be formed over the third polysilicon layer, there would be a substantial absence of nitrogen at the silicide/polysilicon interface and cross-diffusion would probably occur.
It would, therefore, be desirable to provide a method for fabricating semiconductor devices, for instance, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface which may be easily incorporated into current fabrication processes and is not prohibitively expensive. Further, it would be desirable to provide a method for fabricating semiconductor devices (e.g., transistors) that include a metal gate strap disposed over the polysilicon layer thereof and which include a hardened gate oxide, the devices characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion.